View EL5306ISZ-T7_6225101.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7357.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2005, 2007, 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners. el5106, el5306 350mhz fixed gain amplifiers with enable the el5106 and el5306 are fixed gain amplifiers with a bandwidth of 350mhz. this make s these amplifiers ideal for today?s high speed video and monitor applications. they feature internal gain setting re sistors and can be configured in a gain of +1, -1 or +2. with a supply current of just 1.5ma and the ability to run from a single supply voltage from 5v to 12v, these amplifiers are also ideal for handheld, portable or battery powered equipment. the el5106 and el5306 also incorporate an enable and disable function to reduce the supply current to 25a typical per amplifier. allowing the ce pin to float or applying a low logic level will enable the amplifier. the el5106 is offered in the 6 ld sot-23 and the industry-standard 8 ld soic packages and the el5306 is available in the 16 ld soic and 16 ld qsop packages. all operate over the industrial temperature range of -40c to +85c. features ? pb-free available (rohs compliant) ? gain selectable (+1, -1, +2) ? 350mhz -3db bw (a v = 2) ? 1.5ma supply current per amplifier ? fast enable/disable ? single and dual supply operation, from 5v to 12v ? available in sot-23 packages ? 450mhz, 3.5ma product available (el5108 and el5308) applications ? battery powered equipment ? handheld, portable devices ? video amplifiers ? cable drivers ? rgb amplifiers ordering information part number part marking package pkg. dwg. # el5106iwz-t7* (note 1) bafa (note 2) 6 ld sot-23 (pb-free) p6.064a el5106iwz-t7a* (note 1) bafa (note 2) 6 ld sot-23 (pb-free) p6.064a el5106is 5106is 8 ld soic (150 mil) m8.15e el5106isz (note 1) 5106isz 8 ld soic (150 mil) (pb-free) m8.15e el5106isz-t7* (note 1) 5106isz 8 ld soic (150 mil) (pb-free) m8.15e el5106isz-t13* (note 1) 5106isz 8 ld soic (150 mil) (pb-free) m8.15e el5306isz (note 1) el5306isz 16 ld soic (150 mil) (pb-free) m8.15e EL5306ISZ-T7* (note 1) el5306isz 16 ld soic (150 mil) (pb-free) m8.15e el5306isz-t13* (note 1) el5306isz 16 ld soic (150 mil) (pb-free) m8.15e el5306iuz (note 1) 5306iuz 16 ld qsop (150 mil) (pb-free) mdp0040 el5306iuz-t7* (note 1) 5306iuz 16 ld qsop (150 mil) (pb-free) mdp0040 el5306iuz-t13* (note 1) 5306iuz 16 ld qsop (150 mil) (pb-free) mdp0040 *please refer to tb347 for detai ls on reel specifications. notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 2. the part marking is located on the bottom of the part. data sheet september 21, 2010
2 fn7357.6 september 21, 2010 pinouts el5106 (8 ld soic) top view el5106 (6 ld sot-23) top view el5306 (16 ld soic, qsop) top view 1 2 3 4 8 7 6 5 - + nc in- in+ vs- ce vs+ out nc 1 2 3 6 4 5 - + out vs- in+ vs+ in- ce 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 - + - + - + ina+ cea vs- ceb inb+ nc cec inc+ ina- outa vs+ outb inb- nc outc inc- el5106, el5306
3 fn7357.6 september 21, 2010 absolute maxi mum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . 13.2v pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . v s - -0.5v to v s + +0.5v maximum continuous output current . . . . . . . . . . . . . . . . . . . 50ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s + = +5v, v s - = -5v, r l = 150 , t a = +25c unless otherwise specified. parameter description conditions min typ max unit ac performance bw -3db bandwidth a v = +1 250 mhz a v = -1 380 mhz a v = +2 350 mhz bw1 0.1db bandwidth 20 mhz sr slew rate v o = -2.5v to +2.5v, a v = +2 3000 4500 v/s t s 0.1% settling time v out = -2.5v to +2.5v, a v = 2 16 ns e n input voltage noise 2.8 nv/ hz i n + in+ input current noise 6pa/ hz dg differential gain error (note 3) a v = +2 0.02 % dp differential phase error (note 3) a v = +2 0.04 dc performance v os offset voltage -10 1 10 mv t c v os input offset voltage temperature coefficient measured from t min to t max 5v/c a e gain error v o = -3v to +3v, r l = 150 12.5% r f , r g internal r f and r g 325 input characteristics cmir common mode input range 3 3.3 v +i in + input current 1.5 7 a r in input resistance at i n +2m c in input capacitance 1pf output characteristics v o output voltage swing r l = 150 to gnd 3.4 3.6 v r l = 1k to gnd 3.7 3.85 v i out output current r l = 10 to gnd 60 100 ma supply i son supply current - enabled (per amplifier) no load, v in = 0v 1.35 1.5 1.82 ma i soff supply current - disabled (per amplifier) no load, v in = 0v 12 25 a psrr power supply rejection ratio dc, v s = 4.75v to 5.25v 75 db el5106, el5306
4 fn7357.6 september 21, 2010 enable t en enable time 280 ns t dis disable time 400 ns i ihce ce pin input high current ce = v s +1525a i ilce ce pin input low current ce = v s -+10-1a v ihce ce input high voltage for power-down v s + -1 v v ilce ce input low voltage for enable v s + -3 v note: 3. standard ntsc test, ac signal amplitude = 286mv p-p , f = 3.58mhz electrical specifications v s + = +5v, v s - = -5v, r l = 150 , t a = +25c unless otherwise specified. (continued) parameter description conditions min typ max unit pin descriptions el5106 (so8) el5106 (sot23-6) el5306 (so16, qsop16) pin name function equivalent circuit 1, 5 6, 11 nc not connected 2 4 9, 12, 16 in- inc-, inb-, ina- inverting input circuit 1 331, 5, 8in+ ina+, inb+, inc+ non-inverting input (reference circuit 1) 4 2 3 vs- negative supply 6 1 10, 13, 15 out outc, outb, outa output circuit 2 7 6 14 vs+ positive supply 852, 4, 7ce, cea, ceb, cec chip enable circuit 3 r g r f in- in+ r f out v s + v s - ce el5106, el5306
5 fn7357.6 september 21, 2010 typical performance curves figure 1. frequency response figure 2. frequency response for various c l figure 3. group delay vs frequency figure 4. bandwidth vs supply voltage figure 5. peaking vs supply voltage fig ure 6. power supply rejection ratio vs frequency 100k frequency (hz) 1m 10m 1g normalized gain (db) 1 -1 -3 -5 3 5 100m a v = -1 a v = 1 a v = 2 v s = 5v r l = 150 100k frequency (hz) 1m 10m 1g gain (db) 7 5 3 1 9 11 100m c l = 10pf c l = 6.8pf c l = 2.2pf c l = 0pf a v = +2 v s = 5v r l = 150 1 frequency (hz) 10 100 1k delay time (ns) 0.8 0.4 0 1.2 1.6 a v = 1, 2 a v = -1 r l = 150 4.5 frequency (hz) 5.0 5.5 11.0 bw (mhz) 250 150 350 450 6.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 6.5 a v = -1 a v = 2 a v = 1 r l = 150 v s (v) peaking (db) 0.2 0 0.4 0.6 0.8 1 a v = 1 a v = 2 r l = 150 a v = -1 4.5 5.0 5.5 11.0 6.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 6.5 1k frequency (hz) 10k 100m psrr (db) -80 -60 -40 -20 0 100k 1m 10m psrr+ -10 -30 -50 -70 psrr- psrr (db) el5106, el5306
6 fn7357.6 september 21, 2010 figure 7. output impedance vs frequency figure 8. supply current vs supply voltage (per amplifier) figure 9. harmonic distortion vs frequency figure 10. enabled response figure 11. disabled response figure 12. package power dissipation vs ambient temperature typical performance curves (continued) 10k frequency (hz) 100k 1m 100m impedance ( ) 1 0.1 10 100 10m v s (v) i s (ma) 1.20 1.30 1.40 1.50 1.60 1.55 1.45 1.35 1.25 i s - i s + 4.5 5.0 5.5 11.0 6.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 6.5 0 -10 -20 -40 -50 -80 -90 0m 10m 20m 30m 40m 60m frequency (hz) distortion (db) 50m -70 -30 -60 hd3 hd2 v s = 5v a v = 2 r l = 150 v op-p = 2v ch1 2.00v/div ch2 1.00v/div m=100ns ch1 2.00v/div ch2 1.00v/div m=100ns 1.0 0.9 0.8 0.6 0.4 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 0.7 0.3 0.5 909mw 625mw 633mw 391mw so16 (0.150?) ja = +110c/w so8 ja = +160c/w qsop16 ja = +158c/w sot23-6 ja = +256c/w el5106, el5306
7 fn7357.6 september 21, 2010 applications information product description the el5106 and el5306 are fixed gain amplifier that offers a wide -3db bandwidth of 350mhz and a low supply current of 1.5ma. they work with su pply voltages ranging from a single 5v to 12v and they are also capable of swinging to within 1.2v of either supply on the output. these combinations of high bandwidth and low power make the el5106 and el5306 the ideal choice for many low-power/high-bandwidth applications such as portable, handheld, or battery-powered equipment. for varying bandwidth and higher gains, consider the el5191 with 1ghz on a 9ma su pply current or the el5162 with 300mhz on a 4ma supply current. versions include single, dual, and triple amp packages with 5 ld sot-23, 16 ld qsop, and 8 ld soic or 16 ld soic outlines. power supply bypassing and printed circuit board layout as with any high frequency device, good printed circuit board layout is necessary for optimum performance. low impedance ground plane construction is essential. surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. the power supply pins must be well bypassed to reduce the risk of oscillation. the combination of a 4.7f tantalum capacitor in parallel with a 0.01f capacitor has been shown to work well when placed at each supply pin. disable/power-down the el5106 and el5306 amplifiers can be disabled placing their output in a high impedance state. when disabled, the amplifier supply current is reduced to <25a. the el5106 and el5306 are disabled when its ce pin is pulled up to within 1v of the positive supply . similarly, the amplifier is enabled by floating or pulling the ce pin to at least 3v below the positive supply. for 5v supply, this means that the amplifier will be enabled when ce is 2v or less, and disabled when ce is above 4v. although the logic levels are not standard ttl, this choice of logic voltages allow the el5106 and el5306 to be enabled by tying ce to ground, even in 5v single supply applications. the ce pin can be driven from cmos outputs. gain setting the el5106 and el5306 are built with internal feedback and gain resistors. the internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. figure 14 shows the amplifier in gain of +2 configuration. the gain error is 2% maximum. figure 15 shows the amplifier in gain of -1 configuration. for gain of +1, in+ and in- should be connected together as shown in figure 16. this configuration avoids the effects of any parasitic capacitance on the in- pin. since the internal feedback and gain resistors change with temperature and pr ocess, external resistor should not be used to adjust the gain settings. figure 13. package power dissipation vs ambient temperature typical performance curves (continued) ambient temperature (c) 0 0.4 1.4 1.2 1.0 0.8 0.6 0.2 0 25 50 75 100 150 power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.1 1.250w qsop16 ja = +112c/w 909mw 893mw 435mw so8 ja = +110c/w sot23-6 ja = +230c/w so16 (0.150?) ja = +80c/w figure 14. a v = +2 - + 325 325 in- in+ el5106, el5306
8 fn7357.6 september 21, 2010 supply voltage range and single-supply operation the el5106 and el5306 have been designed to operate with supply voltages having a span of greater than or equal to 5v and less than 11v. in practical terms, this means that the el5106 and el5306 will operate on dual supplies ranging from 2.5v to 5v. with single-supply, the el5106 and el5306 will operate from 5v to 10v. as supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. the el5106 and el5306 have an input range which extends to within 2v of either supply. so , for example, on 5v supplies, the el5106 and el5306 have an input range which spans 3v. the output range is also qu ite large, extending to within 1v of the supply rail. on a 5v supply, the output is therefore capable of swinging from -4v to +4v. single-supply output range is larger because of t he increased negative swing due to the external pull-down resistor to ground. figure 16 shows an ac-coupled, gain of +2, +5v single supply circuit configuration. video performance for good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as dc levels are changed at the output. this is especially difficult when driving a standard video load of 150 , because of the change in output current with dc level. previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variat ions in output impedance). special circuitries have been incorporated in the el5106 and el5306 to reduce the variatio n of output impedance with current output. this results in dg and dp specifications of 0.02% and 0.04, while driving 150 at a gain of 2. output drive capability in spite of its low 1.5ma of supply current per amplifier, the el5106 and el5306 are capable of providing a maximum of 125ma of output current. driving cables and capacitive loads when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, the back-termination series resistor will decouple the el5106 and el5306 from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. in these applications, a small series resistor (usually between 5 and 50 ) can be placed in series with the output to eliminate most peaking. figure 15. a v = -1 - + 325 325 in- in+ figure 16. a v = +1 - + 325 325 in- in+ figure 17. - + 325 325 v in +5 0.1f 1k 1k 0.1f +5 v out el5106, el5306
9 fn7357.6 september 21, 2010 current limiting the el5106 and el5306 have no internal current-limiting circuitry. if the output is short ed, it is possible to exceed the absolute maximum rating for output current or power dissipation, potentially resultin g in the destruction of the device. power dissipation with the high output drive capability of the el5106 and el5306, it is possible to exceed the +125c absolute maximum junction temperature under certain very high load current conditions. generally speaking when r l falls below about 25 , it is important to calc ulate the maximum junction temperature (t jmax ) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the el5106 and el5306 to remain in the safe operating area. these parameters are calculated as shown in equation 1: where: t max = maximum ambient temperature ja = thermal resistance of the package n = number of amplifiers in the package pd max = maximum power dissipation of each amplifier in the package pd max for each amplifier can be calculated as shown in equation 2: where: v s = supply voltage i smax = maximum bias supply current v outmax = maximum output voltage (required) r l = load resistance t jmax t max ja npd max () + = (eq. 1) pd max 2 ( v s i smax ) v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2 ) revision history date revision change 6/4/09 fn7357.6 removed obsolete, leaded devices el5106iw-t7, el5106iw-t7a; el5106is-t7, el5106is- t13; el5306is, el5306is-t7, el5306is-t13; el5306iu, el5306iu-t7, el5306iu-t13 corrected figure references in ?gain setting? on page 7 (fig 14 callout was referencing fig 13; fig 15 callout was referencing fig 14; fig 16 callout was referencing fig 15) . updated pin descriptions to match pin names of el5306. applied intersil standards: updated pb-free bu llet in features, updated ordering information by removing tape and reel column and adding standard reference note and updating note to match lead finish, updated caution statement to legal's suggested verbiage. changed date and rev'd to 6. updated pod mdp0038 top6.064a - p6.064a replaces 6 ld sot-23 (same dimensions, just mdp0038 had both 5 & 6 ld sot23s w/dimensions listed in table) updated pod mdp0027 to m8.15e - m8.15e replaces mdp0027 8 ld soic (same dimensions, just mdp0027 had 8, 14, 16, 20, 24, 28 ld soics with dimensions listed in table) p1, added note 2 "the part marking is located on the bottom of the part" for sot-23 package el5106, el5306
10 fn7357.6 september 21, 2010 el5106, el5306 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
11 fn7357.6 september 21, 2010 el5106, el5306 package outline drawing p6.064a 6 lead small outline transistor plastic package rev 0, 2/10 1.60 0.08-0.20 see detail x (0.60) 0-3 3 5 detail "x" side view typical recommended land pattern top view end view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 1.45 max c b a d 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 64 5 5 13 2 plane dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7357.6 september 21, 2010 el5106, el5306 quarter size outline plast ic packages family (qsop) 0.010 c a b seating plane detail x e e1 1 (n/2) (n/2)+1 n pin #1 i.d. mark b 0.004 c c a see detail "x" a2 44 gauge plane 0.010 l a1 d b h c e a 0.007 c a b l1 mdp0040 quarter size outline plastic packages family symbol inches tolerance notes qsop16 qsop24 qsop28 a 0.068 0.068 0.068 max. - a1 0.006 0.006 0.006 0.002 - a2 0.056 0.056 0.056 0.004 - b 0.010 0.010 0.010 0.002 - c 0.008 0.008 0.008 0.001 - d 0.193 0.341 0.390 0.004 1, 3 e 0.236 0.236 0.236 0.008 - e1 0.154 0.154 0.154 0.004 2, 3 e 0.025 0.025 0.025 basic - l 0.025 0.025 0.025 0.009 - l1 0.041 0.041 0.041 basic - n 16 24 28 reference - rev. f 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.

▲Up To Search▲

Price & Availability of EL5306ISZ-T7

	To Download EL5306ISZ-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .